Operating System Architecture (proposed)
Codename: UOS v1r1, Mon 2 Aug
1 Introduction
2 System resource limitations
3 Instruction pipeline
4 I/D-caches
5 Memory, I/O device interface
6 CPU Architecture
7 Exception/fault handling
8 Interrupt vector table
9 Instruction set architecture
10 BIOS architecture
1. Introduction
This document outlines the technical implementation details for UOS (Unazed Ope rating System) as of the date outlined in the heading. Introduced merely to rec oncile my present day understanding of operating systems, and satiate my boredo m.
2. System resource limitations
UOS will implement fixed size memory/disk interfaces, subset by the host hardwa re. The word size is 64 bits. The instruction cache is 16 words in size (1K). The data cache is 4096 words (65K), it is an associative array associating addr esses with data.
Note:
Half-word: 32 bits, short: 16 bits, byte: 8 bits
3. Instruction pipeline
The CPU will incorporate an instruction pipeline, i.e. FIFO byte-queue, to allo w for variable-length decoding of instructions, as per the custom instruction s et architecture mandates.
Instruction bytes will feed from the instruction cache, unless a branching inst ruction is executed upon which the CPU will trigger a page fault at the branchi ng address.
Once an instruction (stream of valid instruction bytes) is fed, control will be delegated to the arithmetic/logic unit, or control unit, to perform calculatio ns, or modify CPU state.
4. I/D-caches
The CPU will incorporate both (I)nstruction/(D)ata caches in order to minimize heavy-duty I/O requests, thereby speeding up data retrieval.
The instruction cache is populated once UOS initializes CPU state, entering ins tructions beginning at the BIOS entry point, then either once (a) the instructi on pointer reaches beyond the scope of the i-cache (b) a branching instruction is fed into the pipeline–the i-cache will invalidate.
Once an instruction is executed which prompts modification of memory/disk space , the data cache will populate pertaining addresses with the corresponding mod ified data; then, once an instruction prompting data retrieval is fed into the pipeline, the relevant data will be retrieved from the d-cache.
5. Memory, I/O device interface
The CPU will NOT implement on-board paging tables, nor memory segmentation. The BIOS will begin executing in a flat memory system, with predefined interrupt t ables that handle page faults (triggering direct disk I/O.)
If a kernel developer wishes to, they may implement their own paging system by overriding the page fault vector, corresponding with their own page tables and virtualizing the address space, but the calculation will be done in-kernel.
I/O devices may be communicated with via the instruction set’s port instruction s; the devices will have access to memory/disk I/O through means of their own c ustom interrupt vectors, which must be registered and acknowledged by the perta ining device.
By doing so, a kernel developer may virtualize/memory-map a slot of memory for the device.
6. CPU Architecture
The CPU will implement registers as follows:
DTYPE SIZE NAME D-QUALS
| < shadowed subregisters >
\ ...
The specification mandates the following registers exist as such:
data W r0 RW
| data HW rhw0
| data S rs0
\ data B rb0
.
.
.
data W r3 RW
| data HW rhw3
| data S rs3
\ data B rb3
state W ip RW*
*indirectly writeable
state S cr RW* (2)
*indirectly writeable
state W sp RW
state B flags R (1)
(1) The FLAGS register looks as follows:
BITS
8........7........6........5.........4........3........2........1.........0
/-------------------------------------------------------------------------\
| Zero | Greate | Remain | Parity | Reserv | Reserv | Reserv | Reserve |
| | r than | der | | ed | ed | ed | d |
| | | | | | | | |
\-------------------------------------------------------------------------/
(2) The CR/control register looks as follows:
BITS
16.......15.......14.......13........12.......11.......10.......9.........8
/-------------------------------------------------------------------------\
| | |
| Major version | Minor version |
| | |
\-------------------------------------------------------------------------/
BITS (cont.)
8........7........6........5.........4........3........2........1.........0
/-------------------------------------------------------------------------\
| In exc | IVT mo | Reserv | Reserve | Reserv | Reserv | Reserv | Reserve |
| eption | dified | ed | d | ed | ed | ed | d |
| | | | | | | | |
\-------------------------------------------------------------------------/
On power-up, the CPU will initialize itself by:
(1) Nulling general-purpose registers (r0-r3), stack pointer, flags
(2) Initializing control register to predefined hardware values
(3) Running pre-BIOS checks, ensuring:
(a) RAM is operable, collecting size statistics
(b) storage medium (floppy disk, VFS, etc.) exists and is operable
(c) graphics driver compatibility, and operability
(4) Loading BIOS from internal storage into RAM, based at 0x0
(5) Read IVT from 0x0 until NULL entry
(6) Begin code execution at 0x800
7. Exception/fault handling
During instruction execution, the CPU may encounter the following exceptions/fa ults:
EXC NO. EXC CODE EXC REASON
-> POST-EXC STATE
0x00 EDIV Division by zero
-> set r0 to faulting execution address
0x01 EPAGE Page fault
-> set r0 to faulting execution address
set r1 to address being accessed
0x02 EUSER User-invoked exception (1) (2)
-> set r0 to faulting execution address
0x03 EINST Illegal instruction
-> set r0 to the faulting execution address
(1) The CPU must preserve general-purpose register state unless otherwise speci fied once transitioning state from CPU to (if) registered interrupt excepti on handler; e.g., user-invoked exceptions may pass error-codes in rb1.
(2) User-invoked exceptions MUST copair with registered interrupt handlers, if the CPU does not record an IVT entry then the CPU will return state to the faulting execution address
If an exception handler is not registered by the developer, then the CPU will r
esort to hanging after attempting to dump the issue. Otherwise, a developer may
invoke the stexc instruction following (1) exception number and (2) the inte
rrupt number.
8. Interrupt vector table format
Each interrupt vector table (IVT) entry is word-sized, i.e. 64 bits. The CPU recognizes the following format for interrupt vectors:
BYTES
8.ID.....7.FLAGS..6.OFFSET.5.........4........3........2........1.........0
/-------------------------------------------------------------------------\
| INT. |E*****UE| Near offset for interrupt trampoline |
| ID |X*****SX| or primary interrupt handler code (1) |
| 0-255 |T*****RC| |
\-------------------------------------------------------------------------/
(2)
(1) The offset is limited to 2^48 as is assumed that the kernel developer will implement a kernel interrupt trampoline table that is close in physical/vir tual memory.
(2) (a) * denotes strictly reserved to NULL bits
(b) The EXT flag depicts the interrupt as strictly externably callable, the
refore any userland interrupt calls to the interrupt will result in an
exception
(c) The EXC flag denotes an IVT entry as an exception handler, indicating i
f the CPU encounters an exception and this entry is copaired, it will r
elegate the relevant information to this handler
(d) The USR flag is to be FALSE if EXC is FALSE, otherwise it depicts wheth
er or not the exception handler is for handling user-invoked exceptions
The IVT can be viewed by copy using the LIVT interrupt, otherwise once the BIO S passes control to the developer, the IVT may be overwritting using:
movw $NEW_IVT, %r0
movb $NUMBER_IVT_ENTRIES, %rb1
int $SIVT_INT_NO
In which event the CPU will call its predefined SIVT interrupt, overwrite itsel f, and pass control back to the developer. The developer MUST implement his own SIVT/LIVT interrupts if he wishes to modify it in the future.
9. Instruction set architecture
The instruction set architecture is RISC, variable length instructions. An inst ruction byte is at least one byte. Following is the instruction template:
OPCODE { OPERAND-n (OPERAND-n D-TYPES)? } *
imm Immediate value, dtype must correspond with source register, if any
data-reg Data register, anything with RW(*) DATA-QUALS, e.g., r0-r3 and sp
reg-offs Constant/linear register offset, e.g., `a * r2 + b`
memory Memory unit corresponding with other operand/instruction dtype, pro
mpts memory I/O
b/s/hw/w byte/short/half-word/word
+ ... signed d-type
And following is the instruction set:
Data move
1 mov SOURCE DESTINATION
mov imm b/s/hw/w data-reg
mov imm b/s/hw/w memory
mov data-reg - data-reg
mov data-reg - memory
mov reg-offs b/s/hw/w data-reg
mov reg-offs b/s/hw/w memory
mov memory - data-reg
Unconditional direct branch
2 jmp DESTINATION
jmp imm w
jmp reg-offs w
jmp memory w
jmp data-reg w
Unconditional IP-relative branch
3 jmprel DESTINATION
jmprel imm +w
jmprel reg-offs +w
jmprel memory +w
jmprel data-reg +w
Stack push, decrement sp by sizeof op-1 dtype
4 push SOURCE
push imm b/s/hw/w
push data-reg b/s/hw/w
push memory b/s/hw/w
Stack pop, increment sp by sizeof op-1 dtype
5 pop DESTINATION
pop data-reg b/s/hw/w
Unsigned arithmetic addition
6 add SOURCE DESTINATION
add imm b/s/hw/w data-reg
add data-reg - data-reg
add reg-offs b/s/hw/w data-reg
add memory b/s/hw/w data-reg
add imm b/s/hw/w memory
add reg-offs b/s/hw/w memory
Unsigned arithmetic multiplication
7 mul SOURCE DESTINATION
mul imm b/s/hw/w data-reg
muk data-reg - data-reg
mul reg-offs b/s/hw/w data-reg
mul memory b/s/hw/w data-reg
mul imm b/s/hw/w memory
mul reg-offs b/s/hw/w memory
Unsigned arithmetic subtraction
8 sub SOURCE DESTINATION
sub imm b/s/hw/w data-reg
sub data-reg - data-reg
sub reg-offs b/s/hw/w data-reg
sub memory b/s/hw/w data-reg
sub imm b/s/hw/w memory
sub reg-offs b/s/hw/w memory
Unsigned arithmetic division
9 div SOURCE DESTINATION
div imm b/s/hw/w data-reg
div data-reg - data-reg
div reg-offs b/s/hw/w data-reg
div memory b/s/hw/w data-reg
div imm b/s/hw/w memory
div reg-offs b/s/hw/w memory
Logical OR
10 or SOURCE DESTINATION
or imm b/s/hw/w data-reg
or data-reg - data-reg
or reg-offs b/s/hw/w data-reg
or memory b/s/hw/w data-reg
or imm b/s/hw/w memory
or reg-offs b/s/hw/w memory
Logical AND
11 and SOURCE DESTINATION
and imm b/s/hw/w data-reg
and data-reg - data-reg
and reg-offs b/s/hw/w data-reg
and memory b/s/hw/w data-reg
and imm b/s/hw/w memory
and reg-offs b/s/hw/w memory
Logical exclusive OR
12 xor SOURCE DESTINATION
xor imm b/s/hw/w data-reg
xor data-reg - data-reg
xor reg-offs b/s/hw/w data-reg
xor memory b/s/hw/w data-reg
xor imm b/s/hw/w memory
xor reg-offs b/s/hw/w memory
Invoke interrupt
13 int INT-NO
int data-reg b
int imm b
Pair exception with interrupt handler
14 stexc EXC-NO INT-NO
stexc data-reg b imm b
stexc imm b data-reg b
stexc data-reg b data-reg b
stexc imm b imm b
10. BIOS architecture
The BIOS must implement the following interrupts:
INT. NO INT. DESCRIPTION
REG PARAMS PARAM DESCRIPTION
...
0x00 Write character to console
rb0 ASCII character
rb1 Console row
rb2 Console column
-> set flags.zero on success
0x01 Load IVT to memory
r0 Memory address to load IVT
-> set r0 to number of entries
set flags.zero on success
0x02 Store IVT from memory (1)
r0 Memory address to read IVT
rb1 Number of entries
-> set flags.zero on success
0x03 Modify IVT entry flags
rb0 Interrupt number
rb1 XOR mask
-> set flags.zero on success
(1) The BIOS will need to store its initial IVT from 0x0, followed by a NULL en try; as it will be loaded automatically by the CPU and size is not specifie d